Publications

		Florent de Dinechin, Martin Kumm Application-Specific Arithmetic - Computing Just Right for the Reconfigurable Computer and the Dark Silicon Era Springer 2024 ISBN 978-3-031-42807-4 (Hardcover), 978-3-031-42808-1 (eBook) Buy at springer.com or Buy at amazon.com
		Kumm, M. Dissertation Multiple Constant Multiplication Optimizations for Field Programmable Gate Arrays, Springer Wiesbaden, Germany 2016 (PhD defense: October 30th, 2015) ISBN 978-3-658-13323-8 see Table of Contents and ask me for a copy of a chapter or Buy at springer.com or Buy at amazon.com

1. N. Fiege, M. Kumm, P. Zipf, Bit-Level Optimized Constant Multiplication Using Boolean Satisfiability, IEEE Transactions on Circuits and Systems I: Regular Papers, 71(1), 249-261, 2024 preprint (copyright IEEE) DOI
2. A. Böttcher and M. Kumm, Towards Globally Optimal Design of Multipliers for FPGAs, IEEE Transactions on Computers, 72(5), 2023, 1261-1273, 2023 preprint (copyright IEEE) DOI
3. M. Kumm, A. Volkova and S. I. Filip, Design of Optimal Multiplierless FIR Filters with Minimal Number of Adders, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Volume 42, 658–671, 2023 preprint, DOI
4. R. Garcia, A. Volkova, M. Kumm, A. Goldsztejn and J. Kühle, Hardware-aware Design of Multiplierless Second-Order IIR Filters with Minimum Adders, IEEE Transactions on Signal Processing, 70, 1673-1686, 2022, preprint, DOI
5. S. Tridgell, M. Kumm, M. Hardieck, D. Boland, D. J. M. Moss, P. Zipf, P. and P. H. W. Leong, Unrolling Ternary Neural Networks, ACM Transactions on Reconfigurable Technology and Systems, 12(4), 1–23, 2019, DOI
6. J. Faraone, M. Kumm, M. Hardieck, L. Xueyuan, D. Boland, and P. H. W. Leong, AddNet: Deep Neural Networks using FPGA-Optimized Multipliers, IEEE Transactions on Very Large Scale Integration Systems (TVLSI), 28(1), 115-128, 2020, DOI
7. M. Garrido, K. Möller, M. Kumm, World's Fastest FFT Architectures: Breaking the Barrier of 100 GS/s, IEEE Transactions on Circuits and Systems I: Regular Papers, Volume 66 , Issue 4, 2019, DOI, preprint (copyright IEEE)
8. M. Kumm, Optimal Constant Multiplication using Integer Linear Programming, IEEE Transactions on Circuits and Systems II: Express Briefs, Volume 65, Issue 5, May 2018, DOI, preprint (copyright IEEE)
9. M. Kumm and J. Kappauf, Advanced Compressor Tree Synthesis for FPGAs, IEEE Transactions on Computers, Volume 67, Issue 8, Aug. 2018, DOI, preprint (copyright IEEE)
10. K. Möller, M. Kumm, M. Garrido and P. Zipf, Optimal Shift Reassignment in Reconfigurable Constant Multiplication Circuits, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 37, issue 3, 710–714, 2018, DOI
11. M. Kumm, M. Garrido, O. Gustafsson and P. Zipf, Optimal Constant Coefficient Multiplication using Ternary Adders, IEEE Transactions on Circuits and Systems II: Express Briefs, Volume 65, Issue 7, July 2018, DOI, preprint (copyright IEEE), slides from ISCAS'17
12. M. Kumm, M. Hardieck and P. Zipf, Optimization of Constant Matrix Multiplication with Low Power and High Throughput, IEEE Transactions on Computers, Volume 66, Issue 12, 2017, DOI, preprint (copyright IEEE)
13. K. Möller, M. Kumm, M. Kleinlein and P. Zipf, Reconfigurable Constant Multiplication for FPGAs, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2017, 36(6), 927-–937 DOI
14. M. Kumm and P. Zipf, Comment on “High Efficiency Generalized Parallel Counters for Look-Up Table Based FPGAs”, International Journal of Reconfigurable Computing (Hindawi), 1–3, 2016, DOI
15. M. Garrido, P. Källström, M. Kumm, and O. Gustafsson, CORDIC II: A New Improved CORDIC Algorithm, IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 63, no. 2, pp. 186–190, 2016, DOI
16. M. Kumm, D. Fanghänel, K. Möller, P. Zipf, and U. Meyer-Baese, FIR Filter Optimization for Video Processing on FPGAs, EURASIP Journal on Advances in Signal Processing (Springer), pp. 1–18, 2013, DOI
17. M. Kumm, H. Klingbeil, and P. Zipf, An FPGA-Based Linear All-Digital Phase-Locked Loop, IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 57, no. 9, pp. 2487–2497, 2010, DOI, preprint (copyright IEEE)
18. H. Klingbeil, B. Zipfel, M. Kumm, and P. Moritz, A Digital Beam-Phase Control System for Heavy-Ion Synchrotrons, IEEE Transactions on Nuclear Science, vol. 54, no. 6, pp. 2604–2610, 2007, DOI

1. A. Volkova, R. Garcia, F. de Dinechin, M. Kumm, Hardware-optimal digital FIR filters: one ILP to rule them all and in faithfulness bind them, Asilomar Conference on Signals, Systems and Computers, 2023 preprint (copyright IEEE)
2. M. Hardieck, T. Habermann, F. Wagner, M. Mecik, M. Kumm, P. Zipf, More AddNet: A deeper insight into DNNs using FPGA-optimized multipliers, IEEE International Symposium on Circuits and Systems (ISCAS), 2023, preprint (copyright IEEE), DOI
3. T. Habermann, J. Kühle, M. Kumm and A. Volkova, Hardware-Aware Quantization for Multiplierless Neural Network Controllers, Asia Pacific Conference on Circuits and Systems (APCCAS), 2022, preprint, DOI
4. A. Böttcher, M. Kumm, F. de. Dinechin, Resource Optimal Squarers for FPGAs IEEE International Conference on Field Programmable Logic and Application (FPL), 2022, preprint, DOI
5. R. Garcia, A. Volkova, M. Kumm, Truncated Multiple Constant Multiplication with Minimal Number of Full Adders, IEEE International Symposium on Circuits and Systems (ISCAS), 2022, preprint, DOI
6. A. Böttcher, M. Kumm, F. de. Dinechin, Resource Optimal Truncated Multipliers for FPGAs, IEEE Symposium on Computer Arithmetic (ARITH), 2021 preprint
7. L. Sommer, L. Weber, M. Kumm, A. Koch, Comparison of Arithmetic Number Formats for Inference in Sum-Product Networks on FPGAs, International Symposium on Field-Programmable Custom Computing Machines (FCCM), IEEE, 2020, DOI received the best paper award
8. A. Böttcher, K. Kullmann, M. Kumm, Heuristics for the Design of Large Multipliers for FPGAs, IEEE Symposium on Computer Arithmetic (ARITH), 2020 DOI preprint
9. P. Sittel, J. Wickerson, M. Kumm and P. Zipf, Modulo Scheduling with Rational Initiation Intervals in Custom Hardware Design, Asia and South Pacific Design Automation Conference (ASP-DAC), 2020, DOI nominated as best paper award candidate
10. P. Sittel, N. Fiege, M. Kumm and P. Zipf, Isomorphic Subgraph-based Problem Reduction for Resource Minimal Modulo Scheduling, International Conference on Reconfigurable Computing and FPGAs (ReConFig), 2019, DOI preprint
11. G. Gambardella, J. Kappauf, M. Blott, C. Doehring, M. Kumm, P. Zipf and K. Vissers, Efficient Error-Tolerant Quantized Neural Network Accelerators, IEEE Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2019, preprint DOI received the best paper award
12. F. de Dinechin, S. Filip, L. Forget and M. Kumm, Table-Based versus Shift-And-Add Constant Multipliers for FPGAs, IEEE Symposium on Computer Arithmetic (ARITH), 2019, preprint DOI
13. J. Oppermann, P. Sittel, M. Kumm, M. Reuter-Oppermann, A. Koch, O. Sinnen, Design-Space Exploration with Multi-Objective Resource-Aware Modulo Scheduling, European Conference on Parallel Processing (EUROPAR), 2019, preprint, DOI
14. M. Hardieck, M. Kumm, K. Möller and P. Zipf, Reconfigurable Convolutional Kernels for Neural Networks on FPGAs, 27th ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA), Monterey February 2019, preprint (copyright ACM), DOI
15. M. Hardieck, M. Kumm, P. Sittel and P. Zipf, Constant Matrix Multiplication with Ternary Adders, IEEE International Conference on Circuits and Systems (ICECS), Bordeaux, December 2018. preprint, DOI
16. P. Sittel, M. Kumm, J. Oppermann, K. Möller, P. Zipf, A. Koch, ILP-based Modulo Scheduling and Binding for Register Minimization, IEEE International Conference on Field Programmable Logic and Application (FPL), 2018 preprint (copyright IEEE), DOI
17. M. Kumm, O. Gustafson, F. de Dinechin, J. Kappauf and P. Zipf, Karatsuba with Rectangular Multipliers for FPGAs, IEEE Symposium on Computer Arithmetic (ARITH), 2018, preprint (copyright IEEE) received the best paper award, DOI
18. P. Sittel, K. Möller, M. Kumm, P. Zipf, B. Pasca and M. Jervis, Model-Based Hardware Design based on Compatible Sets of Isomorphic Subgraphs, IEEE International Conference on Field-Programmable Technology (FPT), 2017, DOI, preprint (copyright IEEE)
19. M. Kumm, J. Kappauf, M. Istoan and P. Zipf, Resource Optimal Design of Large Multipliers for FPGAs, IEEE International Conference on Computer Arithmetic, 2017, pp. 131–138, DOI, preprint (copyright IEEE), slides
20. M. Kumm, M. Kleinlein, and P. Zipf, Efficient Sum of Absolute Difference Computation on FPGAsIEEE International Conference on Field Programmable Logic and Application (FPL), 2016, pp. 1-4, DOI, preprint (copyright IEEE), slides
21. U. Meyer-Baese, H. Muddu, S. Schinhaerl, M. Kumm, and P. Zipf, Real-time Fetal ECG System Design using Embedded Microprocessors, SPIE Commercial + Scientific Sensing and Imaging, vol. 9871, pp. 987106-1–987106-14, May 2016, DOI
22. M. Faust, M. Kumm, C.-H. Chang, and P. Zipf, Efficient Structural Adder Pipelining in Transposed Form FIR Filters, IEEE International Conference on Digital Signal Processing (DSP), 2015, pp. 311-314, DOI, preprint (copyright IEEE), slides
23. M. Kumm, S. Abbas, and P. Zipf, An Efficient Softcore Multiplier Architecture for Xilinx FPGAs, IEEE Symposium on Computer Arithmetic (ARITH), 2015, pp. 18–25, DOI, preprint (copyright IEEE), slides
24. K. Möller, M. Kumm, M. Kleinlein, and P. Zipf, Pipelined Reconfigurable Multiplication with Constants on FPGAs, IEEE International Conference on Field Programmable Logic and Application (FPL), 2014, pp. 1–6, DOI, preprint (copyright IEEE)
25. M. Kumm and P. Zipf, Pipelined Compressor Tree Optimization Using Integer Linear Programming, IEEE International Conference on Field Programmable Logic and Applications (FPL), 2014, pp. 1–8, DOI, preprint (copyright IEEE), slides
26. M. Kumm, M. Hardieck, J. Willkomm, P. Zipf, and U. Meyer-Baese, Multiple Constant Multiplication with Ternary Adders, IEEE International Conference on Field Programmable Logic and Application (FPL), 2013, pp. 1–8, DOI, preprint (copyright IEEE), slides
27. M. Kumm, K. Möller, and P. Zipf, Partial LUT Size Analysis in Distributed Arithmetic FIR Filters on FPGAs, IEEE International Symposium on Circuits and Systems (ISCAS), 2013, pp. 2054–2057, DOI, preprint (copyright IEEE)
28. M. Kumm, K. Möller, and P. Zipf, Reconfigurable FIR Filter Using Distributed Arithmetic on FPGAs, IEEE International Symposium on Circuits and Systems (ISCAS), 2013, pp. 2058–2061, DOI, preprint (copyright IEEE)
29. U. Meyer-Baese, G. Botella, D. Romero, and M. Kumm, Optimization of High Speed Pipelining in FPGA-Based FIR Filter Design Using Genetic Algorithm, Proceedings of SPIE, 2012, pp. 1–12, DOI
30. M. Kumm and P. Zipf, Hybrid Multiple Constant Multiplication for FPGAs, IEEE International Conference on Electronics, Circuits and Systems (ICECS), 2012, pp. 556–559, DOI, preprint (copyright IEEE), slides
31. M. Kunz, M. Kumm, M. Heide, and P. Zipf, Area Estimation of Look-Up Table Based Fixed-Point Computations on the Example of a Real-Time High Dynamic Range Imaging System, IEEE International Conference on Field Programmable Logic and Application (FPL), 2012, pp. 591–594, DOI, preprint (copyright IEEE)
32. M. Kumm, K. Liebisch, and P. Zipf, Reduced Complexity Single and Multiple Constant Multiplication in Floating Point Precision, IEEE International Conference on Field Programmable Logic and Application (FPL), 2012, pp. 255–261, DOI, preprint (copyright IEEE), slides
33. M. Kumm, P. Zipf, M. Faust, and C.-H. Chang, Pipelined Adder Graph Optimization for High Speed Multiple Constant Multiplication, IEEE International Symposium on Circuits and Systems (ISCAS), 2012, pp. 49–52, DOI, preprint (copyright IEEE), slides
34. M. Kumm and P. Zipf, High Speed Low Complexity FPGA-Based FIR Filters Using Pipelined Adder Graphs, IEEE International Conference on Field-Programmable Technology (FPT), 2011, pp. 1–4, DOI, preprint (copyright IEEE)
35. M. Mehler, H. Klingbeil, U. Laier, K.-P. Ningel and M. Kumm, The Damping of Longitudinal Quadrupole Oscillations at GSI, Particle Accelerator Conference (PAC), 2009, S.2195–2197
36. M. Kumm and S. Sanjari, Digital Hilbert Transformers for FPGA-Based Phase-Locked Loops, IEEE International Conference on Field Programmable Logic and Application (FPL), 2008, pp. 251–256, DOI, preprint (copyright IEEE), slides

1. G. Gambardella, J. Kappauf, M. Blott, C. Doehring, M. Kumm, P. Zipf and K. Vissers, Analysis of SEU susceptibility of Quantized Neural Network Hardware Accelerators via Error Injection, IEEE International Workshop on Automotive Reliability Test ART, 2019
2. P. Sittel, J. Oppermann, M. Kumm, A. Koch and P. Zipf, HatScheT: A Contribution to Agile HLS, FPGAs for Software Programmers (FSP) Workshop, Dublin August 2018, preprint
3. P. Sittel, T. Schönwälder, M. Kumm and P. Zipf, ScaLP: A Light-Weighted (MI)LP-Library, 21. Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), March 2018, Tübingen. preprint
4. P. Sittel, M. Kumm, K. Möller, M. Hardieck and P. Zipf, High-Level Synthesis for Model-Based Design with Automatic Folding including Combined Common Subcircuits, Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2017, pp. 7–12, preprint
5. K. Möller, M. Kumm, C.-F. Müller, and P. Zipf, Model-based Hardware Design for FPGAs using Folding Transformations based on Subcircuitsternational Workshop on FPGAs for Software Programmers (FSP), 2015, pp. 7–12, arxiv.org, preprint
6. K. Möller, M. Kumm, B. Barschtipan, and P. Zipf, Dynamically Reconfigurable Constant Multiplication on FPGAs., Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2014, pp. 159–169, preprint
7. M. Kumm and P. Zipf, Efficient High Speed Compression Trees on Xilinx FPGAs, Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2014, pp. 171–182, preprint, slides
8. M. Kumm, K. Möller, and P. Zipf, Dynamically Reconfigurable FIR Filter Architectures with Fast Reconfiguration, International Workshop on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), 2013, pp. 1–8, DOI, preprint (copyright IEEE), slides
9. A. Guntoro, P. Zipf, O. Soffke, H. Klingbeil, M. Kumm and M. Glesner, Implementation of Realtime and Highspeed Phase Detector on FPGA, International Workshop on Reconfigurable Computing (ARC), 2006, Vol. 3985, pp. 1–11, DOI

1. M. Kumm und P Zipf, Verfahren zum Multiplizieren zweier Binärzahlen mit einer programmierbaren Logikanordnung und zur Durchführung des Verfahrens geeignete Logikanordnung, 2015, DPMA
2. M. Kumm und P Zipf, Verfahren zum Berechnen von Funktionswerten mit einer Logikanordnung und zur Durchführung des Verfahrens geeignete Logikanordnung, submitted 2017

1. M. Kumm, Preisgünstige Eigenbau-Lötstation mit SMD-Lötspitze von Weller, Funkamateur, 07/2014
2. M. Kumm, C. Valens, S. Malekar, An SMD solder station made from bits and pieces! Platino Solder Station, Elektor 07-08/2015
3. M. Kumm, C. Valens, S. Malekar, Bauen Sie Ihre eigene SMD-Lötstation! Platino-Lötkolben, Elektor (Germany) 07-08/2015